Meeting date: 07 mar 2006
Members (asterisk for those attending):
Arpad Murayni,
*Bob Ross,
Todd Westerhoff,
*Mike LaBonte,
Paul Fernando,
*Barry Katz,
*Walter Katz,
Ken Willis,
Ian Dodd
Lance Wang

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Review of ARs:

AR: Mike make the website more outsider-friendly
- TBD

AR: Todd contact Cadence about a new representative
- no report

AR: Mike finish documentation examples.
- in progress

AR: Todd contact Ian
- no report

AR: Arpad look at Walter's model
- Walter incorporated comments and resent to group.

AR: Arpad make buffers scalable

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Philosophical issues
- Use B element in some complicated way.
- 2 models:
  - Intel multi-stage
    - One I/V curve, multiple states
    - Each state is a different scaling of the I/V
  - Xilinx RocketIO from Mentor
    - polynomial I/V
- Haven't seen either one
- Need to ask Arpad about zero-denominator problems
  in scaled I/V curves

What is the purpose of IBIS macro?
- Netlists calling macros can work in any simulator with
  minimum translation
- We should provide translators

Intel has released ICH8 model directly in AMS

Overclocking
- Not an issue with 2-B-element multistage
- Problem if trying to use macros for 4 state model
  - Fixed delay for inverting 2nd driver
  - Jittered stimulus causes a problem.
  - Need to model emphasis buffer accurately.
  - Requires a state machine.

AMS-written B elements vs. native B elements
- Arpad's implementations can be used by non-IBIS simulators
- We expect IBIS simulators to call B elements directly
- Passing raw data instead of file=, model= makes this difficult.
- We should be able to create buffers with custom K(t) function
- Can BIRD95 be implemented around B element?
  - Not sure.

Ambrish Varma suggested implementing BIRD95 in a macromodel
- Are macromodels for non-IBIS things or to get ahead of IBIS?
- Can try it using existing macros, write a new macro if it doesn't work.

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Next meeting: Tuesday 14 mar 2006 12:00pm PT